Design of a New Chip Architecture for a Home Gateway

نویسندگان

  • Kwang-Soon Choi
  • Kwang-Mo Jung
  • Myung-Hyun Yoon
چکیده

As Internet is becoming popular to everyone recently, demands for higher-quality services such as VOD and home networking have been increasing. Especially, home networking system can interconnect and control home appliances which use different protocols via Internet. This means that a common protocol to communicate with each other and a new system architecture to implement the common protocol are needed. In this paper, we propose a common protocol and a novel chip architecture with a memory management scheme for a home gateway system. Key-Words: Common Protocol, Packet Conversion, Home Gateway, Home Network, Shared Memory

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

دروازه اطلاعات علمی،‌پژوهشی، و فناورانه ایران: خدمتی نوین برای پژوهشگران ایرانی

Information Subject Gateways are providing access to the necessary quality controlled databases among the vast resources for users of the web and saving them from the confusion and perplexity among the sources on the web. The main objective of this research is creating Iranian Gateway for Scientific, Research, and Technological Information as a valuable source for use by academics and researche...

متن کامل

Drug Discovery Acceleration Using Digital Microfluidic Biochip Architecture and Computer-aided-design Flow

A Digital Microfluidic Biochip (DMFB) offers a promising platform for medical diagnostics, DNA sequencing, Polymerase Chain Reaction (PCR), and drug discovery and development. Conventional Drug discovery procedures require timely and costly manned experiments with a high degree of human errors with no guarantee of success. On the other hand, DMFB can be a great solution for miniaturization, int...

متن کامل

Design of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems

Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing core...

متن کامل

A Novel and Efficient Hardware Implementation of Scalar Point Multiplier

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical path...

متن کامل

Design of a Fuzzy Controller Chip with New Structure, Supporting Rational-Powered Membership Functions

In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2002